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MDT1005
1. General Description
This ROM-Based 8-bit micro-controller uses a fully static CMOS design technology combines higher speed and smaller size with the low power and high noise immunity of CMOS. On chip memory system includes 0.5 K bytes of ROM, and 32 bytes of static RAM. u Sleep Mode for power saving u 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler u 4 types of oscillator can be selected by programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator u 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms
2. Features
The followings are some of the features on the hardware and software : u Fully CMOS static design u 8-bit data bus u On chip ROM size : 512 words u Internal RAM size : 32 bytes (25 general purpose registers, 7 special registers) u 36 single word instructions u 14-bit instructions u 2-level stacks u Operating voltage : 2.3V ~ 6.3 V u Operating frequency : 0 ~ 20 MHz u The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction u Addressing modes include direct, indirect and relative addressing modes u Power-on Reset u Power edge-detector Reset
u On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely u Pull up resistors for the following pins : PA0~PA3, PB0~PB7, /MCLR, RTCC u Pull down resistors for the following pins : PA0~PA3, PB0~PB7, RTCC u 12 I/O pins with their own independent direction control
3. Applications
The application areas of this MDT1005 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.1
2005/6
Ver1.4
MDT1005
4. Pin Assignment
PA2 PA3 RTCC /MCLR Vss PB0 PB1 PB2 PB3
1 2 3 4 5 6 7 8 9
18 17 16 15 14 13 12 11 10
PA1 PA0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
5. Pin Function Description
Pin Name PA0~PA3 PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss I/O I/O I/O I I I O Function Description Port A, TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground
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P.2
2005/6
Ver1.4
MDT1005
6. Memory Map
(A) Register Map Address 00 01 02 03 04 05 06 07~1F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Internal RAM, General Purpose Register
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2
Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A8
A7~A0
Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.3
2005/6
Ver1.4
MDT1005
(4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5X7 Symbol C HC Z PF TF XX Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit General purpose bits Function
(5) MSR (Memory Select Register) : R4 (6) PORT A : R5 PA3~PA0, I/O Register (7) PORT B : R6 PB7~PB0, I/O Register (8) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1 : 16 1:8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Prescaler assignment bit : 0 X RTCC 1 X Watchdog Timer RTCC signal Edge : 0 X Increment on low-to-high transition on RTCC pin 1 X Increment on high-to-low transition on RTCC pin RTCC signal set : 0 X Internal instruction cycle clock 1 X Transition on RTCC pin
2X0
PS2X0
3
PSC
4
TCE
5
TCS
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P.4
2005/6
Ver1.4
MDT1005
(9) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" x"0", I/O pin in output mode; x"1", I/O pin in input mode. (10) Configuration ROM G Bit 1 0 0 1 1 Bit 0 0 1 0 1 Oscillator Type RC Oscillator
LFXT Oscillator XTAL Oscillator HFXT Oscillator
Bit 3 0 0 1 1
Bit 2 0 1 0 1
Oscillator Start-up Time 150 s 20 ms 40 ms 80 ms
Bit 4 0 1 Bit 5 0 1 (B) Program Memory Address 000-1FF 1FF
Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time Power Edge-detector Disable Enable
Description Program memory The starting address of the power onA external reset or WDT
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P.5
2005/6
Ver1.4
MDT1005
7. Reset Condition for all Registers
Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B Address 00h 01h 02h 03h 04h 05h 06h Power-On Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 111x xxxx - - - - xxxx xxxx xxxx /MCLR or WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 111u uuuu - - - - uuuu uuuu uuuu
Note : uxunchanged, xxunknown, - xunimplemented, read as "0" #xvalue depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 u 1 0 0 Status: bit 3 u 0 1 0
8. Instruction Set
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO R STWR R LDR R, t Function No operation Clear Watchdog timer Sleep mode Load W to TMODE register Return Control I/O port register Store W to register Load register Operating None 0/WT 0/WT,stop OSC W/TMODE Stack/PC W/CPIO r W/R R/t TF, PF TF, PF None None None None Z Status
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P.6
2005/6
Ver1.4
MDT1005
Instruction Code 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr Mnemonic Operands LDWI I Function Load immediate to W Operating I/W [R(0~3) R(4~7)]/t R + 1/t R + 1/t W + R/t R W/t (R+/W+1/t) R 1/t R 1/t R a W/t i a W/W R a W/t i a W/W R o W/t i o W/W /R/t R(n)/R(n-1), C/ R(7), R(0)/C R(n)/r(n+1), C/R(0), R(7)/C 0/W 0/R 0/R(b) 1/R(b) Skip if R(b)=0 Skip if R(b)=1 n/PC, PC+1/Stack n/PC n/PC, PC+1/Stack Stack/PC,i/W n/PC Status None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C
SWAPR R, t Swap halves register INCR R, t Increment register
INCRSZ R, t Increment register, skip if zero ADDWR R, t Add W and register SUBWR R, t Subtract W from register DECR R, t Decrement register
DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI i IORWR R, t IORWI i XORWI i RRR R, t AND W and immediate Inclu. OR W and register Inclu. OR W and immediate Exclu. OR W and immediate Rotate right register
XORWR R, t Exclu. OR W and register COMR R, t Complement register
010101 trrrrrrr
RLR
R, t
Rotate left register
C
010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr 1000nn nnnnnnnn 1010nn nnnnnnnn 110000 nnnnnnnn 110001 iiiiiiii 11001n nnnnnnnn
CLRW CLRR BCR BSR R R, b R, b
Clear working register Clear register Bit clear Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address
Z Z None None None None None None None None None
BTSC R, b BTSS R, b LCALL n LJUMP n CALL RTWI JUMP n i n
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P.7
2005/6
Ver1.4
MDT1005
Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : : Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive ` a' Exclusive ` o' Logic AND ` a' : : 0 1 R: C: HC : Z: / : x : i : n: b t Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
9. Electrical Characteristics
(A) Operating Voltage & Frequency Vdd R 2.3 V ~ 6.3 V FrequencyR Hz ~ 20 MHz 0 (B) Input Voltage @ V ddx 5.0 V, Temperaturex25 J Port Vil Vih PA, PB RTCC, /MCLR PA, PB RTCC, /MCLR Min. Vss Vss 2.0 V 3.5 V Max. 1.0 V 0.8 V Vdd Vdd
Threshold Voltage : Port A, Port B V thx 1.54 V RTCC, /MCLR V il x 1.35 V, V ih x 2.85 V (Schmitt Trigger) (C) Output VoltageR @ V ddx 5.0 V, Temperaturex25 J, the typical value as followings : PA, PB Port Iohx 20.0 mA Iol x 20.0 mA Iohx 5.0 mA Iol x 5.0 mA (D) Leakage Current
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Vohx 3.50 V Vol x 0.60 V Vohx 4.60 V Vol x 0.25 V
P.8
2005/6
Ver1.4
MDT1005
@ V ddx 5.0 V, Temperaturex25 J, the typical value as followings : Iil Iih 1.0 A (Max.) I 1.0 A (Max.)
(E) Sleep Current @WDTDisable, Temperaturex25 J, the typical value as followings : Vddx 2.3 V ~6.3V
d d O
I
1.0A
@WDTEnable, Temperaturex25 J, the typical value as followings : Vddx 2.3 V Vddx 3.0 V Vddx 4.0 V Vddx 5.0 V Vddx 6.3 V (F) Operation Current Temperaturex25 J, the typical value as followings : (i) OSC TypexRC ; WDTEnable; @ V ddx 5.0 V Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 10.26 M 6.00 M 1.476 M 724.4 K 242.4 K 151.6 K 5.12 M 2.774 M 640.0 K 307.6 K 101.2K 63.68 K Current (A) 1.35 m 790.0 230.0 135.0 70.0 60.0 680.0 390.0 125.0 78.0 55.0 50.0 IddO 1.0 A Iddx 1.2 A Iddx 4.0 A Iddx 12.0 A Iddx 20.0 A
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P.9
2005/6
Ver1.4
MDT1005
Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 1.53 M 781.2 K 172.4.0K 82.0 K 27.0 K 17.0 K 633.6 K 322.4 K 69.60 K 33.04 K 10.8 K 6.84 K Current (A) 240.0 140.0 65.0 50.0 47.0 45.0 125.0 85.0 55.0 50.0 45.0 43.0
(ii) OSC TypexLF (C=20 p); WDTDisable; PED-Disable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.3 V 32 K 4.0 A 6.0 A 15.0 A 30.0 A 40.0 A 455 K X 50.0 A 70.0 A 120.0 A 180.0 A 1M X 80.0 A 125.0 A 200.0 A 250.0 A Sleep O1.0 A O1.0 A O1.0 A O1.0 A O1.0 A
(iii) OSC TypexXT (C=10 p); WDTEnable; PED-Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V 1M 65.0 A 130.0 A 220.0 A 330.0 A 530.0 A 4M 210.0 A 360.0 A 620.0 A 980.0 A 1.7 mA 10 M 480.0 A 760.0 A 1.25 mA 1.80 mA 2.70 mA Sleep O1.0 A 1.2 A 4.0 A 12.0 A 20.0 A
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P.10
2005/6
Ver1.4
MDT1005
(iv) OSC TypexHF (C=10 p); WDTEnable; PED-Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.3 V (G) Pull Resistance @ Input Mode : V ddx 3.0 V PORT RTCC /MCLR Pull-High Pull-Low Pull-High Pull-Low Resistance Resistance Resistance Resistance R x 300.0 KOhm hi R x 300.0 KOhm lo R x 280.0 KOhm hi R x 280.0 KOhm lo Rhi x 150.0 KOhm 4M 190.0 A 350.0 A 670.0 A 1.1 mA 1.9 mA 10 M 420.0 A 740.0 A 1.3 mA 2.0 mA 3.0 mA 20 M
@2.3v900.0A
Sleep O0.1 A 1.2 A 4.0 A 12.0 A 20.0 A
1.40 mA 2.2 mA 3.2 mA 4.7 mA
Pull-High Resistance
@ Input Mode : V ddx 5.0 V PORT RTCC /MCLR Pull-High Pull-Low Pull-High Pull-Low Pull-High Resistance Resistance Resistance Resistance Resistance R x 100.0 KOhm hi R x 100.0 KOhm lo R x 110.0 KOhm hi R x 110.0 KOhm lo R x 100.0 KOhm hi
p.s. : It is only a reference value for the Pull High/Low Resistance, and the accurate value of the Resistance depends on the various parameter of the Process. But the variation of the value will be not more than 20%.
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P.11
2005/6
Ver1.4
MDT1005
(H) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ V ddx 5.0 V VprO 1.1~1.3 V Vpr
R
Vdd (Power Supply)
(I) The basic WDT time-out cycle time Temperaturex25 J, the typical value as followings : Voltage (V) 2.3 3.0 4.0 5.0 6.3 Basic WDT time-out cycle time (ms) 34.00 27.60 23.20 20.40 18.00
(J) MCLRB FilterG Vdd=5.0v @ Wm O1.2us Wm : Filter pulse width (low) in /MCLR pin.
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P.12
2005/6
Ver1.4
MDT1005
10. Port A and Port B Equivalent Circuit
Working Register
D QB
Data I/P
I/O Control
CK
I/O Control Latch
Q
MOS Pull-Hi (Long Channel)
Information Sheet Pull Hi/Lo Selection
Port I/O Pin
D
Write
CK
Data O/P Latch
Q
MOS Pull-Down (Long Channel)
Data Bus
QB D
Read
Data I/P Latch
CK
Input Resistor TTL Input Level
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P.13
2005/6
Ver1.4
MDT1005
11. MCLRB and RTCC Input Equivalent Circuit
MOS Pull Hi (Long Channel)
R U 1 K
MCLRB Schmitt Trigger
Information Sheet Pull Hi/Lo Selection
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P.14
2005/6
Ver1.4
MDT1005
MOS Pull Hi (Long Channel)
R U 1 K
RTCC Schmitt Trigger
MOS Pull Low (Long Channel)
Information Sheet Pull Hi/Lo Selection
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P.15
2005/6
Ver1.4
MDT1005
12. Block Diagram
Stack Two Levels
ROM 512N14
RAM 25N8 Port A
Port PA0~PA3 4 bits
9 bits 9 bits 14 bits
Program Counters
Instruction Register
Special Register
D0~D7 OSC1 OSC2 MCLR
Port B Instruction Decoder
Port PB0~PB7 8 bits
Oscillator Circuit
Control Circuit
Data 8-bit
Power on Reset Power Down Reset Working Register ALU Status Register
8-bit Timer/Counter
Prescale
WDT/OST Timer
RTCC
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P.16
2005/6
Ver1.4
MDT1005
13. Capacitor Selection For Crystal Oscillator
(a) With built-in Oscillation Capacitors ( Default for HF,XT,LF ) @ V ddx 2.3V~5.5 V , C1=C2=10P~15P
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P.17
2005/6
Ver1.4
MDT1005
(b) Without built-in Oscillation Capacitors @ V ddx 3.0 V~ 5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K C1 5 pF ~10 pF 10 pF ~50 pF 10 pF ~50 pF 10 pF ~30 pF 10 pF ~50 pF 10 pF ~30 pF 3 pF ~5 pF 10 pF ~30 pF 10 pF ~20 pF C2 10 pF~30 pF 20 pF ~100 pF 20 pF ~100 pF 10 pF ~50 pF 20 pF ~100 pF 20 pF ~50 pF 3 pF ~5 pF 20 pF ~50 pF 15 pF ~30 pF
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P.18
2005/6
Ver1.4
MDT1005
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor range are recommended, but the higher capacitance will increase the start-up time. There do not have built-in Oscillation Capacitors for RC type.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P.19
2005/6
Ver1.4

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